The present invention relates to a semiconductor apparatus and substrate and in particular to a semiconductor apparatus including alignment marks and a substrate having the semiconductor apparatus formed thereon.
A single product (semiconductor apparatus) obtained by simultaneously forming, for example, multiple integrated circuits over the main surface of a single semiconductor substrate (wafer) by certain technologies is cut into multiple products (semiconductor chips) on an integrated circuit basis, typically by the technology called dicing. Formed over the main surface of the wafer are so-called alignment marks. Examples of alignment marks include alignment marks for performing alignment during so-called laser trimming (LT) (alignment marks for LT) and alignment marks for overlaying a photomask on a desired position (alignment marks for overlay). Note that while alignment marks for LT and alignment marks for overlay have different applications, they are not limited to the applications described in the specification of this application. That is, alignment marks described as alignment marks for LT may be used as alignment marks for overlay, and vice versa.
In Japanese Unexamined Patent Application Publication No. 2008-28243, for example, alignment marks are formed over lines (scribe lines) along which a wafer is to be cut during dicing. In Japanese Unexamined Patent Application Publication No. 2006-303073, for example, walls called guard rings are formed in order to control entry of moisture into integrated circuits and corrosion of the integrated circuits.
The guard rings are intended to protect the integrated circuits from the sides (peripheries). On the other hand, a protective film (such as a passivation film, or a polyimide film) may be formed in order to protect the integrated circuits from above. Covering the top surfaces of the integrated circuits with a protective film allows the integrated circuits to be protected from moisture or sediment. A semiconductor apparatus including such protective film is disclosed in, for example, Japanese Unexamined Patent Application Publication No. 2003-282484.
In Japanese Unexamined Patent Application Publication Nos. 2008-28243 and 2003-282484, alignment marks are formed in positions over scribe lines. Alternatively, alignment marks may be formed in a semiconductor chip, as disclosed in Japanese Unexamined Patent Application Publication No. 2010-129695.
In a semiconductor apparatus of Japanese Unexamined Patent Application Publication No. 2003-282484, for example, a protective film is formed in an area where scribe lines are to be formed (scribe line area). Accordingly, the protective film is cut during dicing. A crack may be formed in the protective film from cut surfaces of these films by external stress. Such a crack in the protective film is known to break the guard ring and thus reduce the moisture resistance of the integrate circuit, as well as to reduce the reliability of the semiconductor chip. For the purpose of dispersing and reducing external stress that causes such a crack or break, Japanese Unexamined Patent Application Publication No. Hei 2(1990)-77131, for example, discloses a semiconductor apparatus having slits formed in guard rings. Japanese Unexamined Patent Application Publication No. 2011-29430, for example, discloses a semiconductor apparatus including guard rings that each include two wiring layers and a via coupling the wiring layers for the same purpose. Japanese Unexamined Patent Application Publication No. 7-201855, for example, discloses a semiconductor apparatus including guard rings that each include a pattern bent in a meandering manner for the same purpose.